1. Field of the Invention:
The present invention relates in general to semiconductor memory devices, especially those having a very large memory capacity. More specifically, the invention is directed to shortening the testing time of a semiconductor memory device.
2. Prior Art:
FIG. 1 (Prior Art) shows a schematical block diagram of an exemplary conventional semiconductor memory device of a fairly large memory capacity, for instance, a 64 K bits random access memory (RAM). Address signals provided via signal lines A0, A1 . . . A7 and signal lines A8, A9 . . . A15 are decoded by the X-decoder 1 and Y-decoder 2 and select a single memory cell in the memory array 3. In a writing cycle, the input data provided through the input/output terminal 4 is controlled by an input/output circuit 5 and is memorized in the selected memory cell. In a reading cycle, the data or information of the selected memory cell is amplified and controlled by the input/output circuit 5 and provided as an output through the terminal 4.
In a testing procedure of a RAM, writings and readings of data into and out of the memory array are carried out, and the read-data are checked, that is the data are compared with expected data. In order to test a large memory, a single writing and reading is not sufficient, because data destruction due to interference of proximity cells or as a result of some addressing way may take place in the RAM. Therefore, testing of as many combinations of data and as many combinations of addressing as possible are necessary. Most general testing methods known for such purpose are "Walking", "Pingpong" and "Gallopping". The testing called "Gallopping" is performed as follows. One memory all of the array is selected and caused to assume a "0" state. All other cells are "1" Data of the appointed cell and of all the rest of the cells are read out alternatingly, and the appointed cell is change to another cell and the process is repeated. The change of appointed memory cell proceeds one after another and this testing requires 6N.sup.2 +6N cycles of writing and reading for a memory of N bits.
When the "Gallopping" testing is made for the conventional RAM, as can be understood from the above formula, the testing time length becomes extraordinarily long as memory capacity becomes large. For instance, when cycle time is 100 NS, the testing time lengths are:
for 4 K bits memory . . . substantially 10 seconds, PA1 16 K bits memory . . . substantially 2 minutes 41 seconds, PA1 64 K bits memory . . . substantially 42 minutes 57 seconds and, PA1 256 K bits memory . . . substantially 11 hours 2 minutes 9 seconds. PA1 a plural number of memory array blocks having common address signal lines and common input/output lines and PA1 the same plural number of comparators for comparing respective output signals of said memory array blocks and common respective expected signals for testing therewith.
By constituting the RAM as 8 blocks construction, the testing time can be shortened to one eighth of the above time length, the time length is still very long.